Floating point type digital signal reversible encoding method, decoding method, devices for them, and programs for them
US7126501B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 27, 2004 |
| Grant date | Oct 24, 2006 |
| Priority date | — |
| Expiry date | Apr 27, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M7/24
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Digital signal samples X in a floating-point format, each of which is composed of 1 bit of sign, 8 bits of exponent E and 23 bits of mantissa M, are converted through rounding by an integer formatting part 12 into digital signal samples Y in an integer format, the sequence of the digital signal samples Y is losslessly compression-coded by a compressing part 13 into a code sequence Ca, and the code sequence Ca is output. The digital signal samples Y are converted by a floating point formatting part 15 into digital signal samples X′ in the floating-point format, a difference signal ΔX indicating the difference between the digital signal sample X′ and the digital signal sample X is determined by a subtraction part 16, the difference signal ΔX is losslessly coded, and the resulting code sequence Cb is output.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.