Read-accessible column latch for non-volatile memories
US7126860B2 · kind B2 · utility
4Cited by
7References
15Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 3, 2005 |
| Grant date | Oct 24, 2006 |
| Priority date | — |
| Expiry date | Jan 3, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/3459
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Program column latch circuitry of nonvolatile memory is provided with read-back capability to verify that data bits have been correctly loaded into the latch circuits and written to the memory cells. The interface between the low voltage latches and the external input and output data paths is provided with opposite-facing tri-state buffers that allow latched data to be read out for comparison and verification. Writing of latched data to memory cells can be verified by the read-back without needing any external RAM.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.