Method and system for expanding flash storage device capacity
US7126873B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 29, 2004 |
| Grant date | Oct 24, 2006 |
| Priority date | — |
| Expiry date | Dec 25, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/02
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Through the use of an allocation logic unit with a Flash controller, a single primary chip enable is de-multiplexed into a multiple secondary chip enables for multiple Flash memory dies or chips. In so doing, Flash storage device capacity is greatly expanded. In a first aspect, a memory package includes a plurality of memories; and an allocation logic unit coupled to the plurality of memories for receiving a single chip enable signal. The allocation logic unit de-multiplexes the single chip enable signal to a plurality of chip enable signals. Each of the plurality of chip enable signals access to one of the plurality of memories.In a second aspect, a printed circuit board (PCB) includes a Flash controller for providing at least one primary chip enable signal. The PCB also includes a plurality of Flash memory chips and at least one allocation logic unit coupled to at least a portion of the plurality of Flash memory chips and the Flash controller. The allocation logic unit receives the at least one chip enable signal and de-multiplexes the at least one chip enable signal to a plurality of secondary chip enable signals. Each of the plurality of chip enable signals controls access to o…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.