Performance optimized approach for efficient downsampling operations
US7127482B2 · kind B2 · utility
46Cited by
3References
10Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 19, 2001 |
| Grant date | Oct 24, 2006 |
| Priority date | — |
| Expiry date | Apr 16, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F17/147
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An algorithm and hardware structure is described for numerical operations on signals that is reconfigurable to operate in a downsampling or non-downsampling mode. According to one embodiment, a plurality of adders and multipliers are reconfigurable via a switching fabric to operate as a plurality of MAAC ( multiply-add-accumulator) kernels (described in detail below), when operating in a non-downsampling mode and a plurality of MAAC kernels and AMAAC (add-multiply-add-accumulator) kernals (described in detail below), when operating in a downsampling mode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.