Method and arrangement for concealing errors
US7127644B2 · kind B2 · utility
0Cited by
4References
4Claims
0Family size
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Key dates
| Filing date | Aug 9, 2001 |
| Grant date | Oct 24, 2006 |
| Priority date | — |
| Expiry date | Aug 17, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11B2020/00065
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A method of concealing errors in a single bit bitstream comprises low pass filtering the bitstream, replacing the low pass filtered signal during an error by a low frequency approximation of the signal and subsequently converting the signal by a ΣΔ-modulator into a regenerated single bit bitstream. During the absence of an error the original bitstream may be outputted and during an error the regenerated bitstream, which is obtained from a ΣΔ-modulator, which is bit-synchronized to the original bitstream.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.