Reconfigurable architecture for decoding telecommunications signals
US7127664B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 18, 2001 |
| Grant date | Oct 24, 2006 |
| Priority date | — |
| Expiry date | Feb 21, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L1/0055
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
The present invention discloses a single unified decoder for performing both convolutional decoding and turbo decoding in the one architecture. The unified decoder can be partitioned dynamically to perform required decoding operations on varying numbers of data streams at different throughput rates. It also supports simultaneous decoding of voice (convolutional decoding) and data (turbo decoding) streams. This invention forms the basis of a decoder that can decode all of the standards for TDMA, IS-95, GSM, GPRS, EDGE, UMTS, and CDMA2000. Processors are stacked together and interconnected so that they can perform separately as separate decoders or in harmony as a single high speed decoder. The unified decoder architecture can support multiple data streams and multiple voice streams simultaneously. Furthermore, the decoder can be dynamically partitioned as required to decode voice streams for different standards.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.