Method for preventing circuit failures due to gate oxide leakage
US7127689B2 · kind B2 · utility
0Cited by
3References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 28, 2004 |
| Grant date | Oct 24, 2006 |
| Priority date | — |
| Expiry date | Feb 3, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/367
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method is disclosed for preventing circuit failures due to gate oxide leakage, and is used to efficiently check many nets of a circuit on a chip or within a macro to find logical fails due to gate oxide leakage using DC calculations, wherein the gate leakage is treated as a noise source for a static noise analysis of the circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.