Charge modulation network for multiple power domains for silicon-on-insulator technology
US7129545B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 24, 2005 |
| Grant date | Oct 31, 2006 |
| Priority date | — |
| Expiry date | Feb 24, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/601
Abstract
An SOI integrated circuit includes ESD protection on an SOI chip. A first power domain and a second power domain are provided in the SOI chip. In one embodiment, a charge modulation network in the SOI chip between the first power domain and the second power domain mitigates accumulation of electrical charge in an electrically isolated region of the SOI chip. In another embodiment, an ESD protection device in the SOI chip electrically connects the first power domain and the second power domain via a low metal layer to provide a discharge path for accumulated charge.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.