Power supply packaging system
US7129577B2 · kind B2 · utility
8Cited by
17References
16Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Feb 27, 2003 |
| Grant date | Oct 31, 2006 |
| Priority date | — |
| Expiry date | Jul 11, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K2201/10674
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A packaging system for a high current, low voltage power supply. The power supply uses bare die power FETs which are directly mounted to a thermally conductive substrate by a solder attachment made to the drain electrode metallization on the back side of the FETs. The source electrode and gate electrode of each FET are coupled to the circuitry on an overhanging printed circuit board, using CSP solder balls affixed to the front side of the FET die. The heat generated by the FETs is effectively dissipated by the close coupling of the FETs to the thermally conductive underlying substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.