At-speed on-chip short clock cycle monitoring system and method
US7129690B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 29, 2005 |
| Grant date | Oct 31, 2006 |
| Priority date | — |
| Expiry date | Dec 29, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F1/04
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention provides a system and method for monitoring a short clock cycle on a semiconductor chip. The system includes a phase-locked loop (PLL) for receiving a reference clock as input and for outputting a PLL clock out. The system includes a delay-locked loop (DLL) for receiving the PLL clock out as input and for outputting a DLL phase offset clock. The DLL is locked to a frequency of the PLL clock out. The system may include an edge comparator for receiving the PLL clock out and the DLL phase offset clock as input. The edge comparator is suitable for monitoring each edge of the PLL clock out and each edge of the DLL phase offset clock, and for reporting a short clock cycle when an edge of the PLL clock out comes before an edge of the DLL phase offset clock.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.