Non-volatile look-up table for an FPGA
US7129748B1 · kind B1 · utility
24Cited by
1References
6Claims
0Family size
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Key dates
| Filing date | Dec 29, 2004 |
| Grant date | Oct 31, 2006 |
| Priority date | — |
| Expiry date | Mar 17, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/17728
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A non-volatile-memory-transistor based lookup table for an FPGA includes a n:1 multiplexer. A non-volatile memory transistor is coupled to each of the n inputs of the multiplexer. The multiplexer has x address inputs wherein 2x=n as is known in the art. The output of the multiplexer is coupled to VCC through a pullup transistor. The gate of the pullup transistor is coupled to the output of an address transition detector circuit that has inputs coupled to the address inputs of the multiplexer. A sense amplifier is coupled to the output of the multiplexer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.