Circuit and method for faster frequency switching in a phase locked loop
US7129791B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Aug 4, 2004 |
| Grant date | Oct 31, 2006 |
| Priority date | — |
| Expiry date | Sep 17, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/1072
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A PLL circuit arrangement includes a first frequency divider connected to a reference frequency source, a second frequency divider connected to the output of an oscillator controlled by the output of a loop filter, a phase/frequency detector that detects phase/frequency differences between the two divider outputs, a charge pump between the detector and the loop filter, a controller providing a changeable divider ratio to the first and/or second frequency divider, and a regulating signal generator that changes the output voltage of the loop filter applied to the oscillator in a controlled manner in response to a change of the divider ratio. The signal generator preferably has inputs connected to outputs of the controller and the frequency dividers, and an output connected to the charge pump and/or the loop filter to accelerate the recharging thereof in response to a change of the divider ratio.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.