Method and apparatus for minimizing threshold variation from body charge in silicon-on-insulator circuitry
US7129859B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 22, 2004 |
| Grant date | Oct 31, 2006 |
| Priority date | — |
| Expiry date | Dec 30, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/0008
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
Circuitry used to de-skew data channels coupling parallel data signals over a communication link employs SOI circuitry that is subject to generating pulse distortion due to the history effect modifying threshold voltages. To substantially eliminate the pulse distortion, data signals are XOR with a repeating scramble data pattern that generates scrambled data with a minimum average ratio of logic ones to logic zeros logic zeros to logic ones. The scrambled data is sent over the communication link and de-skewed in the SOI circuitry with little or no pulse distortion. The scramble data pattern is again generated at the receiver side of the communication link after a delay time to synchronize the logic states of the scramble data pattern that generated the scrambled data with the scrambled data at the receiver side. The delayed scrambled data pattern is again XOR'ed with the scrambled data to recover the data signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.