Electrically word-erasable non-volatile memory device, and biasing method thereof
US7130219B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 25, 2005 |
| Grant date | Oct 31, 2006 |
| Priority date | — |
| Expiry date | Feb 25, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/34
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device formed by an array of memory cells extending in rows and columns. The device is formed by a plurality of N-type wells extending parallel to the rows; each N-type well houses a plurality of P-type wells extending in a direction transverse to the rows. A plurality of main bitlines extend along the columns. Each P-type well is associated to a set of local bitlines that extend along the respective P-type well and are coupled to the drain terminals of the cells accommodated in the respective P-type well. Local-bitlines managing circuits are provided for each P-type well and are located between the main bitlines and a respective set of local bitlines for controllably connecting each local bitline to a respective main bitline.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.