Self-route expandable multi-memory packet switch with distributed scheduling means
US7130301B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 28, 2001 |
| Grant date | Oct 31, 2006 |
| Priority date | — |
| Expiry date | May 22, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L49/506
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
Data transmission system comprising a plurality of Local Area Networks (LANs) (10-1 to 10-4) interconnected by a hub (12) including the same plurality of LAN adapters (16-1 to 16-4) respectively connected to the LANs and a packet switch (14) interconnecting all LAN adapters wherein a packet transmitted by any adapter to the packet switch includes a header containing at least the address of the adapter to which the packet is forwarded. The system comprises a memory block located at each cross point of the switch module for storing any data packet which is received from the input port corresponding to the cross point and which is to be forwarded to the output port corresponding to this cross point, and a scheduler associated with each output port for selecting at each clock time a memory block among all memory blocks corresponding to the output port and causing the memory block to forward the stored data packet to the output port when predetermined criteria are met.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.