Self-route expandable multi-memory packet switch
US7130302B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 28, 2001 |
| Grant date | Oct 31, 2006 |
| Priority date | — |
| Expiry date | Aug 23, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L69/22
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
Data transmission system comprising a plurality of Local Area Networks (LANs) (10-1 to 10-4) interconnected by a hub (12) including the same plurality of LAN adapters (16-1 to 16-4) respectively connected to the LANs and a packet switch (14) comprising at least a packet switch module interconnecting all LAN adapters wherein a packet transmitted by any adapter to the packet switch includes a header containing at least the address of the adapter to which the packet is forwarded. The system comprises a memory block located at each cross point of the switch module including a data memory unit for storing at least a data packet and memory control means for determining from the header of the received data packet whether the packet is to be forwarded to the output port associated with the cross point and for storing the packet into the data memory unit and a scheduler for causing at each clock time a data packet stored in a data memory unit of a memory block among all memory blocks corresponding to the output port to be forwarded to this output port.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.