Data path architecture for a LAN switch
US7130308B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 13, 2001 |
| Grant date | Oct 31, 2006 |
| Priority date | — |
| Expiry date | Jun 30, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L49/354
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A packet switching device having a central shared memory and a number of medium access controllers each coupled to a communications medium to exchange data packets, and a controller coupled to each medium access controller via a data path to exchange data packets with the media access controller. The controller has a number of data path controllers each connected to each medium access controller to exchange a corresponding portion of the data packets with the medium access controller. The data path controllers each have a number of buffers to hold the portion of the data packets exchanged with the corresponding medium access controller. Each data path controller has a selector that selects the buffer from which to exchange the portion of the data packets with the central shared memory and control logic that controls the selector to concurrently select the buffer corresponding to the same medium access controller.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.