Method and device for frame sync detection using channel combining and correlation
US7130333B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 27, 2001 |
| Grant date | Oct 31, 2006 |
| Priority date | — |
| Expiry date | Apr 8, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04B1/7075
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
A method and device for frame sync detection using signal combining and correlation. The method comprises the steps of despreading PN coded signals to provide in-phase I1–In, and quadrature phase Q1–Qn signals, wherein each I1–In and each Q1–Qn signal contains at least one sync bit and n≧2. The at least one sync bit from each I1–In, and quadrature phase Q1–Qn signals are summed to form sums Is1 and Qs1, respectively. The next step provides a reference sync having at least one bit and compares each sum Is1 and Qs1 with the at least one reference bit. The results of each Is1 and Qs1 comparison are accumulated so as to form two accumulates, IA and QA, respectively. Each accumulate IA and QA, is squared to form IA2 and QA2 from which the sum IA2 and QA2 is formed. The sum IA2+QA2 is compared with a predetermined threshold and as a result of the comparison a determination of whether frame sync has been achieved is made.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.