Digital delay lock loop for setup and hold time enhancement
US7130367B1 · kind B1 · utility
7Cited by
3References
8Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 9, 2002 |
| Grant date | Oct 31, 2006 |
| Priority date | — |
| Expiry date | Dec 25, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/0812
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A digital delay lock loop (DLL) circuit for receiving parallel data and clock signals, deserializing the high speed parallel data to low speed data, and for improving setup and hold times. A DLL circuit for an N-bit datapath, includes a clock DLL configured to provide a clock signal pulse within an eye opening of each of N data signals. The DLL circuit further includes N data DLLs, each being configured to adjust a delay of a data signal to substantially center the eye opening of the data signal on the clock signal pulse.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.