Clock recovery using a direct smoothing process
US7130368B1 · kind B1 · utility
240Cited by
7References
17Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 19, 2002 |
| Grant date | Oct 31, 2006 |
| Priority date | — |
| Expiry date | Jan 1, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N21/44004
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A system and method for synchronizing a local clock to a reference clock using a linear model of the error between the local clock and the reference clock is disclosed. In one embodiment, a direct smoothing process is used in conjunction with the linear model to estimate a frequency offset by which the frequency of an oscillator of the local clock is adjusted. Also disclosed herein is a phased-lock loop (PLL) adapted to synchronize a local clock with a reference clock using the direct smoothing process, as well as a system implementing the PLL for timing the playout of data received from a transmitter.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.