First-in first-out memory system with shift register fill indication
US7130984B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 3, 2003 |
| Grant date | Oct 31, 2006 |
| Priority date | — |
| Expiry date | Aug 25, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2205/126
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An electronic device (10). The device comprises a memory structure (12) comprising an integer M of word storage locations. The device further comprises a write shift register (SRWT) for storing a sequence of bits. The sequence in the write shift register comprises a number of bits equal to a ratio of 1/R1 times the integer M. The device further comprises circuitry (16) for providing a write clock cycle to the write shift register for selected write operations with respect to any of the word storage locations. In response to each write clock cycle, received from the circuitry for providing the write clock cycle, the write shift register shifts the sequence in the write shift register. Further, one bit in the sequence in the write shift register corresponds to an indication of one of the memory word storage locations into which a word will be written. The device further comprises a read shift register (SRRD) for storing a sequence of bits. The sequence in the read shift register comprises a number of bits equal to a ratio of 1/R2 times the integer M. The device further comprises circuitry (16) for providing a read clock cycle to the read shift register for selected read operations wi…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.