Parallel processor executing an instruction specifying any location first operand register and group configuration in two dimensional register file
US7130985B2 · kind B2 · utility
1Cited by
11References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 31, 2002 |
| Grant date | Oct 31, 2006 |
| Priority date | — |
| Expiry date | Sep 6, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L9/40
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Described herein is a data processor that comprises a register memory and a processor unit. The processor unit simultaneously executes a single instruction on a plurality of operands in the register memory. The plurality of operands may be one or more contiguous regions. The contiguous regions may be specified as an address and a format such as a row, a column, or a neighborhood relative to the address.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.