Debugger breakpoint management in a multicore DSP device having shared program memory
US7131114B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 15, 2002 |
| Grant date | Oct 31, 2006 |
| Priority date | — |
| Expiry date | Jun 5, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/362
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processing system comprises a digital signal processor (DSP) device and a host system on which the DSP device is implemented. The DSP device comprises a shared program memory and a plurality of processor subsystems coupled to the shared program memory to concurrently execute program instructions stored in the shared program memory. The host system is capable of independently debugging each subsystem. During debugging, the host device inserts breakpoints into the shared program memory and tracks the debug breakpoints to determine which subsystems are associated with the breakpoints. When a subsystem executes a breakpoint associated with that subsystem, the subsystem halts until the host gathers necessary debug information from the subsystem. However, when a subsystem executes a breakpoint that is not associated with that subsystem, the host system causes the subsystem to execute the original program instructions and proceed as directed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.