Method for repairing plasma damage after spacer formation for integrated circuit devices
US7132368B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 26, 2004 |
| Grant date | Nov 7, 2006 |
| Priority date | — |
| Expiry date | Dec 29, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B10/00
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for processing integrated circuit memory devices. The method includes supporting a partially completed substrate, the substrate comprising a plurality of MOS gate structures. Each of the gate structures has substantially vertical regions that define sides of the gate structures. The method forms a conformal dielectric layer overlying the gate structures. The conformal dielectric layer has a predetermined thickness of material that covers each of the gate structures including vertical regions. The method also forms sidewall spacers on the sides of the gate structures from the conformal dielectric layer using an anisotropic etching process and exposes a portion of the substrate region during the formation of the sidewall spacers using the anisotropic etching process to cause physical damage (e.g., plasma damage, cracks) to a portion of the exposed portion of the substrate. The method smoothes exposed portions of the sidewall spacers and exposed portions of the substrate using at least a plasma treatment process including an isotropic etching component to the exposed portion of the substrate and sidewall spacers on the sides of the gate structures whereupon the exposed portio…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.