Power metal oxide semiconductor transistor layout with lower output resistance and high current limit
US7132717B2 · kind B2 · utility
23Cited by
6References
14Claims
0Family size
Assignee
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Key dates
| Filing date | Apr 20, 2005 |
| Grant date | Nov 7, 2006 |
| Priority date | — |
| Expiry date | Apr 20, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/60
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A power metal oxide semiconductor transistor layout is disclosed. The power metal oxide semiconductor transistor layout uses network of conductive lead line as a connection or a network connection to connect source and drain regions thereby achieves advantages of a high uniformity of current, low Rds_on, much less power loss, an actual line density two times larger than that of conventional layouts and a strengthened resistance to electron migration.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.