Layout technique for C3MOS inductive broadbanding
US7132727B2 · kind B2 · utility
2Cited by
117References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 18, 2004 |
| Grant date | Nov 7, 2006 |
| Priority date | — |
| Expiry date | May 18, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An improved cell layout for a C3MOS circuit with inductive broadbanding positions the inductor at a distance from the active region to improve isolation and aligns the edges of the resistor, inductor, and transistor regions near the common edge of adjacent cells to decrease the length of the cell-to-cell interconnect lines.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.