Multi-processor restart stabilization system and method
US7132822B1 · kind B1 · utility
5Cited by
19References
34Claims
0Family size
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Key dates
| Filing date | Feb 28, 2006 |
| Grant date | Nov 7, 2006 |
| Priority date | — |
| Expiry date | Feb 28, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F1/30
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A supervisory system and method including a voltage detection circuit, a status signal interface, a memory, and a supervisory processor configured to predict a pending low power condition, to save status parameters, and to take actions to manage a plurality of processors receiving power from a power source susceptible to low voltage conditions, to stabilize the processors prior to and during a low voltage condition, and to restart the processors based on the status parameters.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.