Mitigating parasitic current that leaks to the control voltage node of a phase-locked loop
US7132865B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 23, 2004 |
| Grant date | Nov 7, 2006 |
| Priority date | — |
| Expiry date | Aug 11, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/093
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Parasitic current at the control voltage node of a phase-locked loop (PLL) can significantly reduce performance of the PLL. Off-state transistors in either the charge pump or the filter can cause this parasitic current. A method of canceling a parasitic current generated by the charge pump in the PLL is described. In this method, a leakage current associated with leaky circuits in the charge pump can be determined. An opposing current can be injected to the control voltage node. This opposing current is equal, but opposite, to the leakage current. A method of eliminating a parasitic current generated by the filter in the PLL is also described. In this method, for each programmable capacitor in an unused state, a unity gain buffer can charge the capacitor to the same potential as the control voltage node, thereby providing the same potential on both sides of the switch.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.