Image sensor circuits including sampling circuits used therein for performing correlated double sampling
US7133074B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 28, 1999 |
| Grant date | Nov 7, 2006 |
| Priority date | — |
| Expiry date | Sep 28, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N25/78
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A CMOS image sensor circuit includes an array of sensing elements which integrate electrical charge according to the light intensity thereon. In order to measure the accumulated charge voltage at the individual sensing elements, and thus obtain the image data from the array, a sampling circuit is provided. The sampling circuit operates using a high-gain amplification stage and an auto-zero amplifier to perform correlated double sampling, which enables non-linear influences which may arise in the array to be reduced in the measuring process. The sampling circuit can also include a sample and hold circuit arranged to account for a feed-through effect arising from pre-charge circuitry in the sensing elements. The sample and hold circuit can be included within the feed-back loop of the high-gain amplification stage for further increases in linear performance.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.