Method and apparatus for accelerated post-silicon testing and random number generation
US7133818B2 · kind B2 · utility
1Cited by
6References
20Claims
0Family size
Assignee
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Key dates
| Filing date | Apr 17, 2003 |
| Grant date | Nov 7, 2006 |
| Priority date | — |
| Expiry date | Dec 24, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/318342
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A method of providing accelerated post-silicon testing for a silicon hardware includes computing a simulation cumulative record of state using a plurality of test instructions and a cycle breakpoint, performing a simulation of an instrumented logic design using the plurality of test instructions and the cycle breakpoint, manufacturing the silicon hardware using the instrumented logic design, computing a silicon cumulative record of state by executing the plurality of instructions using the silicon hardware; and comparing the simulation cumulative record of state to the silicon cumulative record of state.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.