Data paths with receiver timing fixable to a downstream stage and methods of operation thereof
US7134034B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Oct 15, 2003 |
| Grant date | Nov 7, 2006 |
| Priority date | — |
| Expiry date | Dec 8, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/02
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A data path includes a downstream stage that strobes data at an input thereof responsive to a first control signal, an upstream stage that sends data to the input of the downstream stage responsive to a second control signal, and a control circuit operative to fix timing of the second control signal to timing of the first control signal. The data path may further include a second upstream stage that sends data to an input of the first upstream stage responsive to a third control signal having a timing with respect to the second control signal that varies responsive to a frequency at which data is transferred along the data path. A fixed delay circuit, e.g., a fixed delay circuit in a forward path of a DLL or PLL, may generate the first control signal from the second control signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.