Static timing analysis approach for multi-clock domain designs
US7134062B2 · kind B2 · utility
5Cited by
8References
27Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Aug 12, 2003 |
| Grant date | Nov 7, 2006 |
| Priority date | — |
| Expiry date | Oct 11, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/3312
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for analyzing a circuit design is disclosed. The method generally includes the steps of (A) determining a plurality of paths from a first clock at a first location to a plurality of second clocks at a plurality of second locations in the circuit design, (B) calculating a plurality of delays along the paths and (C) calculating a plurality of latencies with respect to the first clock for the second clocks using the delays.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.