High speed clock and data recovery system
US7135905B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 12, 2004 |
| Grant date | Nov 14, 2006 |
| Priority date | — |
| Expiry date | Jan 29, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/0025
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A clock and data recovery system for detecting and resolving meta-stability conditions is provided. The clock and data recovery system includes a phase detector having logic configured to detect a meta-stability condition and to generate an output signal to mitigate the condition. The system can also include a time varying gain adjustment portion. This portion includes a gain control logic configured to determine and adjust system gain during reception of an incoming data stream. The system further includes a phase interpolator having increased linearity. The phase interpolator has a plurality of first branches having a differential transistor pair, a switch, and a current source, coupled between a first output and a first supply voltage and a plurality of second branches having a differential transistor pair, a switch, and a current source, coupled between a second output and the first supply voltage. The phase interpolator can also include an integrator portion.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.