Input stage resistant against high voltage swings
US7135908B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jan 29, 2003 |
| Grant date | Nov 14, 2006 |
| Priority date | — |
| Expiry date | May 9, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/00315
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An input stage includes a signal input (IN) for receiving an input signal s(t) and a digital input stage (15) designed for operation at a supply voltage (VDD). The input stage (15) includes CMOS transistors, which are sensitive to voltages across transistor nodes going beyond a voltage limit (Vmax) and an input (IINV). Voltage limiting circuitry (B) is arranged between the signal input (IN) and the input (IINV). The voltage limiting circuitry (B) includes an input switch (ns) controllable by the state of the input signal s(t), and limit voltages at the input (IINV) to the supply voltage (VDD). In addition, over-voltage protection (A) is provided between the signal input (IN) and the supply voltage (VDD). The circuitry for over-voltage protection (A) includes at least one active circuit element arranged so as to mimic part of a zener function.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.