Digitally adjustable amplifier for integrated circuit
US7135916B2 · kind B2 · utility
1Cited by
4References
11Claims
0Family size
Inventor
Key dates
| Filing date | Aug 7, 2003 |
| Grant date | Nov 14, 2006 |
| Priority date | — |
| Expiry date | Aug 7, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F2200/321
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A digitally adjustable amplifier with adjustable input offset voltage and amplification parameters for use in integrated circuits. Such adjustments are carried out by a binary counter which controls a non-binary weighting element which by a non-binary weighting of each stage to the next stage intentionally has a non-linearity of the ideal characteristic curve because of greater negative steps at increasing value count so that the steps remain below one least significant bit. Thus greater errors even can be tolerated, and a desired value can be very closely attained.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.