Bias voltage circuit with ultra low output impedance
US7135929B1 · kind B1 · utility
19Cited by
8References
2Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 21, 2004 |
| Grant date | Nov 14, 2006 |
| Priority date | — |
| Expiry date | Apr 21, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F3/19
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A bias voltage circuit with ultra low output impedance. The circuit incorporates feedback to reduce the output impedance at both low and RF frequencies. The bias circuit outputs a bias signal for biasing an amplifier. The bias circuit includes an input stage that receives an input signal and produces the bias signal at an output terminal that is coupled to a gain stage. The bias circuit also includes a load coupled to the input stage at a first terminal, and a feedback circuit coupled between the first terminal and the gain stage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.