Selective offset adjustment of a track and hold circuit
US7136000B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 17, 2005 |
| Grant date | Nov 14, 2006 |
| Priority date | — |
| Expiry date | Jun 17, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C27/024
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A track/hold circuit with an offset adjustment that can be used to compensate for offset errors from other parts of the system containing the track/hold circuit. The offset adjustment may be provided by impressing a voltage at an electrode of a capacitor of the track/hold circuit during a hold mode and not impressing the voltage at the capacitor electrode during the track mode. The offset adjustment signal may be generated using an adjustable current source to propagate a current through a resistance that is coupled to the track/hold circuit output node via a capacitor of a voltage capacitive divider circuit during the hold mode. The offset introduced into the track/hold mode output signal can be independent of the voltage stored in the voltage capacitive divider circuit just prior to adding the offset adjustment signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.