Embedded multilayer printed circuit
US7136274B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 28, 2004 |
| Grant date | Nov 14, 2006 |
| Priority date | — |
| Expiry date | Oct 28, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K2201/09672
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
An embedded multilayer printed circuit includes a first ground plane (105, 1205, 1405) of a multilayer printed circuit board and an embedded layer. The embedded layer includes a co-planar capacitor (110, 1210, 1410), a distributed inductor (125, 1215, 1415), and a capacitive plate (135, 1220, 1420) circuit. The capacitive plate is a plate of a vertical capacitor (270, 1305, 1505). The embedded layer further includes a node (111, 1225, 1425) of the embedded multilayer printed circuit that is formed by a connection of a first terminal of the co-planar capacitor and a first terminal of the first distributed inductor, and in some embodiments, the first capacitive plate is also connected to the node. A second terminal of one of the co-planar capacitor and the distributed inductor is connected to the first ground plane.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.