Method and apparatus for using address traps to pace writes to peripheral devices
US7136944B2 · kind B2 · utility
0Cited by
8References
15Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Dec 2, 2004 |
| Grant date | Nov 14, 2006 |
| Priority date | — |
| Expiry date | May 1, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/24
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system and method for pacing writes to a legacy peripheral device includes a control block configured to trap on the address of the legacy peripheral device and slows the rate that the CPU posts writes to avoid backpressure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.