Apparatus, system, and method for bus link width optimization
US7136953B1 · kind B1 · utility
178Cited by
1References
23Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 7, 2003 |
| Grant date | Nov 14, 2006 |
| Priority date | — |
| Expiry date | Dec 18, 2024 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A bus permits the number of active serial data lanes of a data link to be re-negotiated in response to changes in bus bandwidth requirements. In one embodiment, one of the bus interfaces triggers a re-negotiation of link width and places a constraint on link width during the re-negotiation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.