Method and apparatus for improving reliability in microprocessors
US7137028B2 · kind B2 · utility
4Cited by
7References
15Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Feb 27, 2004 |
| Grant date | Nov 14, 2006 |
| Priority date | — |
| Expiry date | Jul 16, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/1641
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and system provides an increased robustness and protection against the occurrence of soft errors in parallel connect functional redundancy checking processors. This is achieved by predicting in advance the likely occurrence of a soft error and its impact on the resulting instruction flow and using already existing circuit implementations to hide the transient error.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.