System and apparatus for scanning integrated circuits with numerically controlled delay lines
US7137054B2 · kind B2 · utility
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2References
31Claims
0Family size
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Key dates
| Filing date | Apr 22, 2003 |
| Grant date | Nov 14, 2006 |
| Priority date | — |
| Expiry date | Oct 4, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/3202
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A system and method for scan testing an NCDL and latches controlled by the NCDL is presented. The NCDL is controlled by control logic, a switch is used to control the latches by a clock signal that is not controlled by the control logic. A controllability circuit provides test vectors to, and controls, the NCDL. The outputs of the NCDL are observed by an observability circuit that captures the outputs of the NCDL.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.