Layout method of semiconductor integrated circuit, layout structure thereof, and photomask for forming the layout structure
US7137092B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Aug 10, 2004 |
| Grant date | Nov 14, 2006 |
| Priority date | — |
| Expiry date | Jan 18, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A plurality of standard cells 10 are arranged to form a channel-less standard cell array 1, which has vertical and horizontal sides. A plurality of first proximity dummy cells 20 are arranged along each of the vertical sides of the standard cell array to form a first proximity dummy bands 20 such that the upper and lower sides of the first proximity dummy cells are in contact with each other and such that the left or right side of each of the first proximity dummy cells is in contact with the vertical side of the standard cell array 1. Furthermore, a plurality of second proximity dummy bands are arranged along each of the horizontal sides of the standard cell array to form a second proximity dummy bands such that the upper or lower side of each of the second proximity dummy cells is in contact with the horizontal side of the standard cell 1.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.