Semiconductor device and method for fabricating the same
US7138312B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 3, 2006 |
| Grant date | Nov 21, 2006 |
| Priority date | — |
| Expiry date | May 3, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/038
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The semiconductor device comprises a gate interconnection 24a including a gate electrode formed over a semiconductor substrate 14 with a gate insulation film 22 formed therebetween; a first source/drain diffused layer 28 formed near the end of the gate interconnection 24a; a second source/drain diffused layer 34 formed remote from the gate interconnection 24a and the first source/drain diffused layer 28; and an insulation film 40 formed over the gate interconnection 24a, the first source/drain diffused layer 28 and the second source/drain diffused layer 34, and having a groove-shaped opening 42a formed in, which integrally exposes the gate interconnection 24a, one of the first source/drain diffused layer 28, and one of the second source/drain diffused layer 34; and a contact layer 48a buried in the groove-shaped opening 42a. The groove-shaped openings 42a for the contact layers 48a to be buried in can be formed without failure. Accordingly, it is possible to provide a semiconductor device which can realize the micronization without reliability decrease and fabrication yield decrease.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.