Phase-locked loops
US7138839B2 · kind B2 · utility
6Cited by
7References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 19, 2004 |
| Grant date | Nov 21, 2006 |
| Priority date | — |
| Expiry date | Jul 1, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/187
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A phase-locked loop (PLL) is disclosed. One embodiment, among others, includes a PLL that provides a control current and varies the control current in proportion to an inverse of N squared. N is the ratio of the output frequency of the PLL system to the reference frequency of the PLL system. The varying of the control current compensates for bandwidth changes of the PLL system.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.