Programmable phase shift and duty cycle correction circuit and method
US7138841B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 16, 2004 |
| Grant date | Nov 21, 2006 |
| Priority date | — |
| Expiry date | Feb 1, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2005/00156
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A phase shift and duty cycle correction circuit is disclosed herein as comprising a programmable digital to analog converter (DAC), a storage device (e.g., a capacitor), a charge sub-circuit and dump sub-circuit for charging and discharging the storage device, respectively, a comparator, and a clock driver circuit. A linearly increasing (or ramped) voltage waveform is generated within the storage device by the charging and discharging actions of the charge and dump sub-circuits; a periodic process which is controlled by opposite phases of the input clock. By programming the DAC control input to change the slicing threshold of the ramped waveform, the circuit and method described herein provides a means for programmable phase shifting and duty cycle correction.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.