Variable delay circuitry
US7138844B2 · kind B2 · utility
8Cited by
5References
21Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 18, 2005 |
| Grant date | Nov 21, 2006 |
| Priority date | — |
| Expiry date | Mar 18, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2005/00058
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Circuitry for providing an input data signal to other circuitry on an integrated circuit includes a course delay chain and a fine delay chain. These two delay chains are cascadable, if desired, to provide a very wide range of possible amounts of delay which can be finely graded by use of the fine delay chain.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.