High-gain synchronizer circuitry and methods
US7138850B1 · kind B1 · utility
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99Claims
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Key dates
| Filing date | Aug 3, 2004 |
| Grant date | Nov 21, 2006 |
| Priority date | — |
| Expiry date | Aug 3, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K5/135
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
High-gain synchronizer circuitry and methods are provided that reduce the meta-stable resolve time of a synchronizer circuit. The high-gain synchronizer is made up of high-gain latch circuits. The high-gain latch circuits are made up of a series of inverters that at least initially increase in size and that are connected in a closed loop. In accordance with the invention, the time that the high-gain synchronizer remains in the meta-stable state is minimized through the use of the high-gain latch circuits.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.