Thin film transistor array panel
US7139043B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 7, 2004 |
| Grant date | Nov 21, 2006 |
| Priority date | — |
| Expiry date | May 11, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG02F1/1393
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
A thin film transistor array panel is provided, which includes: a substrate; a gate line formed on the substrate; first and second storage electrodes formed on the substrate and disposed opposite each other with respect to the gate line; a gate insulating layer formed in the gate line and the first and the second storage electrodes; a curved data line formed on the gate insulating layer; a thin film transistor connected to the gate line and the data line; a passivation layer formed on the data line and the thin film transistor; a pixel electrode formed on the passivation layer, connected to the thin film transistor, and having an obtuse corner and an acute corner; and an overpass cross over the gate line and connected to the first and the second storage electrodes.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.