Logical arrangement of memory arrays
US7139183B2 · kind B2 · utility
8Cited by
9References
14Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 21, 2004 |
| Grant date | Nov 21, 2006 |
| Priority date | — |
| Expiry date | Oct 10, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C5/063
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An aspect of the present invention is a logical arrangement of memory arrays. The logical arrangement includes a plurality of memory arrays deposed in a row-column configuration, a controller coupled to the plurality of memory arrays and at least one power line, at least one sense line and at least one address line coupled to the controller wherein a number of connections from the controller to the at least one power line, the at least one sense line and the at least one address line is minimized.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.